System for multiple input floating gate structures

ABSTRACT

The present invention provides a system for efficiently producing versatile multiple input floating gate structures. The present invention provides multiple-input floating gate device ( 100, 400 ) that has a first input ( 106, 406 ) formed in a first active device region ( 202, 502 ) and a second input ( 108, 408 ) formed in a second active device region ( 204, 504 ). A floating gate ( 200, 500 ) is disposed upon the first and second inputs, separated from the inputs by a dielectric layer. A device body, formed in a third active device region ( 210, 506 ), is coupled to the first and second inputs through the floating gate.

PRIORITY CLAIM

[0001] This patent application claims priority of U.S. ProvisionalApplication No. 60/344,513, filed on Dec. 28, 2001.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to the field ofsemiconductor devices, and more particularly to a system for producingmultiple input floating gate (MIFG) devices in a single poly process.

BACKGROUND OF THE INVENTION

[0003] The continual demand for enhanced integrated circuit performancehas resulted in, among other things, a dramatic reduction ofsemiconductor device geometries, and continual efforts to optimize theperformance of every substructure within any semiconductor device. Anumber of improvements and innovations in fabrication processes,material composition, and layout of the active circuit levels of asemiconductor device have resulted in very high-density circuit designs.Increasingly dense circuit design has not only improved a number ofperformance characteristics, it has also increased the importance of,and attention to, semiconductor material properties and behaviors. Assemiconductor device geometries are continually scaled downward, certainproblems arise with fundamental performance characteristics of certaindevice features.

[0004] Consider, for example, a simple MOS-based transistor. One keyperformance parameter for such a device is its threshold voltage(V_(t)). Generally, V_(t), as measured across the gate of a transistor,is fixed. The precise value of V_(t) is generally affected by a numberof layout and process variables, such as the gate oxide thickness andthe dopants utilized. Once a given V_(t) is determined, operation of thetransistor may be simplified to the relationship between V_(t) and thegate voltage (V_(g)). Generally, if the magnitude of V_(g) is greaterthan the magnitude of V_(t), the transistor will turn on, and viceversa. In larger geometry device processes, this typically posed littleconcern because the overall device supply voltage was large enough toaccommodate even a substantial V_(t) value.

[0005] However, as process geometries and, correspondingly, devicesupply voltages have decreased, large V_(t) values have become moreproblematic. Typically, V_(t) values do not scale down in proportion toother device features and parameters when process geometries are“shrunken”. Depending upon the magnitude of a geometry reduction, thisphenomenon can result in a V_(t) that consumes most of the availablesupply voltage range. Usually, in purely digital applications fabricatedin mature processes, this is still not too much of a concern. Because apurely digital device or structure only needs to turn “off” or “on”,minimal supply voltage range exceeding V_(t) is required to achievenecessary performance. Excessively large V_(t) values, however, stillremain problematic for low-power processes, even in purely digitalapplications. This problem is of even greater concern in the design andfabrication of low-power mixed-signal devices (i.e. devices having bothanalog and digital circuitry).

[0006] Often, the analog portions of mixed-signal devices require someactive operating range, commonly referred to as headroom, within whichto operate. In situations where V_(t) consumes most or essentially allof a low-power device's supply voltage range, active headroom isminimized or effectively eliminated altogether. This phenomenon causes anumber of design and performance problems for mixed-signal devices.Designers of analog circuitry, especially low-power analog circuitry,therefore generally prefer a very low V_(t) value. Furthermore, in someapplications it may even be desirable to have a dynamically adjustableV_(t).

[0007] A solution to the excessive V_(t) problem is the use of multipleinput floating gate (MIFG) structures. With typical MIFGs, a singletransistor is implemented with two or more gates that control thecurrent across the transistor and effectively divide the burden ofdriving the device past V_(t). One or more of the gate inputs can becoupled to a constant voltage, while one or more remaining gate inputsare left open for dynamic inputs from other circuitry. Thus, theeffective V_(t) at those open inputs is substantially reduced, leavinggreater headroom. Depending upon the application, multiple inputs may beleft open to provide the ability to dynamically modulate V_(t) for thedevice. In some applications, the MIFG structure may be configured insuch a way as to render V_(t) negative (i.e., depletion mode).

[0008] Although, in theory, MIFG structures are very useful, mostconventional implementations of such structures typically utilize orrequire more complex processes (i.e., dual poly processes) forsuccessful implementation. Generally, in these dual polyimplementations, a first poly layer is utilized in forming conventionalgate structures. The second poly layer, separated from the first poly bysome dielectric (e.g., TEOS, Ni, ONO), is then utilized in forming themultiple gate inputs. In some instances, the need for MIFG structuresmay justify the use of such complex and costly processes. In mostdesigns that could benefit from MIFG structures, however, cost,performance, or fabrication process limitation concerns, in addition todesign process complexities, limit, if not preclude, the feasibility ofusing a dual poly process.

[0009] As a result, there is a need for a system for producing multipleinput floating gate structures in an easy, efficient and cost-effectivemanner.

SUMMARY OF THE INVENTION

[0010] The present invention provides a versatile system for producingmultiple input floating gate (MIFG) structures in an easy, efficient andcost-effective manner. More specifically, the present invention providesa system for producing MIFG structures in a number of low-cost,high-volume MOS fabrication processes. The present invention providesfor MIFG structures in a single poly process, without adding complexityor cost to the design process. The present invention provides multipleinput gate structures formed in a separate active region (e.g., moat),with a poly layer used to provide a floating gate between inputs and MOScircuitry. This system renders extremely efficient MIFG structure designpractical in a number of low-cost, low-power technologies.

[0011] More specifically, the present invention provides a multipleinput floating gate device comprising a first input formed in a firstactive device region and a second input formed in a second active deviceregion. A floating gate disposed upon the first and second inputs,separated therefrom by a dielectric layer. A device body, formed in athird active device region, is coupled to the first and second inputsthrough the floating gate.

[0012] The present invention also provides a MOS transistor, having adynamically adjustable threshold voltage value, comprising a first inputformed in a first active device region and a second input formed in asecond active device region. A floating gate is disposed upon the firstand second inputs, and separated therefrom by a gate oxide. A devicebody is formed in a third active device region, and coupled to the firstand second inputs through the floating gate.

[0013] The present invention further provides a method of producing asemiconductor device, having a dynamically adjustable threshold voltagevalue. The method includes forming a first input in a first activedevice region and forming a second input in a second active deviceregion. A floating gate is disposed upon the first and second inputs,with a dielectric layer interposed therebetween. A device body is formedin a third active device region, and coupled to the first and secondinputs through the floating gate.

[0014] The present invention also provides a method of producing amultiple input floating gate device in a single-poly MOS process. Themethod includes: providing a substrate upon which the device is to befabricated; performing n-well or p-well implant on the substrate;utilizing a LOCOS or STI formation for device isolation; optionallyperforming a high-dose multiple input moat implant; performing thresholdimplant; performing gate oxidation; performing poly gate deposition; andperforming source/drain implantation.

[0015] Other features and advantages of the present invention will beapparent to those of ordinary skill in the art upon reference to thefollowing detailed description taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For a better understanding of the invention, and to show by wayof example how the same may be carried into effect, reference is nowmade to the detailed description of the invention along with theaccompanying figures in which corresponding numerals in the differentfigures refer to corresponding parts and in which:

[0017]FIG. 1 is an illustration of one embodiment of a multiple inputfloating gate device according to the present invention;

[0018]FIG. 2 is an illustration of one embodiment of the multiple inputfloating gate device in FIG. 1 according to the present invention;

[0019]FIG. 3 is an illustration of one embodiment of the multiple inputfloating gate device in FIG. 1 according to the present invention;

[0020]FIG. 4 is an illustration of one embodiment of a multiple inputfloating gate device according to the present invention;

[0021]FIG. 5 is an illustration of one embodiment of the multiple inputfloating gate device in FIG. 4 according to the present invention; and

[0022]FIG. 6 is an illustrative plot depicting data descriptive ofvarious embodiments of multiple input floating gate devices according tothe present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] While the making and using of various embodiments of the presentinvention are discussed in detail below, it should be appreciated thatthe present invention provides many applicable inventive concepts, whichcan be embodied in a wide variety of specific contexts. The inventionwill now be described in conjunction with any memory. The specificembodiments discussed herein are merely illustrative of specific ways tomake and use the invention and do not limit the scope of the invention.

[0024] The present invention provides a versatile system for producingmultiple input floating gate (MIFG) structures in an easy, efficient andcost-effective manner. More specifically, the present invention providesa system for producing MIFG structures in a number of low-cost,high-volume MOS fabrication processes. The present invention providesfor MIFG structures in a single poly process, without adding complexityor cost to the design process. The present invention provides multipleinput gate structures formed in a separate active region (e.g., moat),with a polysilicon (poly) layer used to provide a floating gate betweeninputs and MOS circuitry. In the present invention, a standard MOS gateoxide may be used as a dielectric between the input and floating gates.This system renders extremely efficient MIFG structure design practicalin a number of low-cost, low-power technologies.

[0025] In contrast to the present invention, conventional MIFGstructures are, typically, designed and fabricated in processes havingmore complex, multi-poly/dielectric, modules that are used to build themultiple input gates and provide isolation between the input and thefloating gates. These modules are often not available in many of thehigh-volume, low-cost, fabrication technologies.

[0026] According to the present invention, however, MIFG structures aredesigned and fabricated using standard, low-cost, MOS processes withoutsuch complex modules. Conventional poly 2 input gate structures arereplaced with moat region structures, and the dielectric between theinput and floating gates is replaced with standard MOS gate oxide.

[0027] Utilizing the MIFG structures of the present invention,designers—especially mixed signal designers—are able to fine tune V_(t).This provides designers the ability to design for maximum headroom,especially in low power applications (e.g., 1.8 or even 1.0 volts). Insome cases, the value of the effective V_(t) may even be renderednegative (i.e., depletion mode), improving noise characteristics of thedesign. Of critical importance, however, is capacitance matching betweenthe floating gates. Most often, capacitance matching is addressed indevice layout, as capacitance is functionally related to area of thegates. If gate capacitances are not properly matched, dynamic control ofV_(t) will be complex, as V_(t) will not vary in a regular (i.e.,linear) fashion. This will complicate designs relying on dynamic V_(t)control. Alternatively, however, this aspect may be exploited should anon-linear variance in V_(t) be desired.

[0028] In some embodiments of the present invention, multiple gates arelaid out as copies of a single base gate to ensure perfect matching.Furthermore, to reduce moat depletion effects, highly doped moat regionsmay be used, if available. In the alternative, or in addition, toutilizing highly doped moat regions, poly fingers with minimum channellengths may be utilized.

[0029] All such aspects are now discussed in greater detail withreference to the illustrative embodiments depicted in FIGS. 1-6.Referring now to FIG. 1, a simple conceptual illustration of an MIFGstructure 100 according to the present invention is depicted. Structure100 is a MOS transistor, comprising a source 102 and drain 104.Structure 100 further comprises a first input 106, second input 108,third input 110, and Nth input 112. FIGS. 2 and 3 illustrate alternativetop-view layouts of structure 100. In the embodiment illustrated in FIG.2, a poly region 200 is formed as a floating gate. Multiple input gates106-112 are implemented as multiple active area (moat) regions 202-208,respectively. Source 102 and drain 104 (the MOS body) are implemented inmoat region 210. Floating gate 200 is laid out to effectively andefficiently couple regions 202-210, and interposed therebetween (notshown) is an appropriate material (e.g, gate oxide) to serve adielectric function.

[0030] In an alternative embodiment, illustrated in FIG. 3, separatepoly regions 300 and 302 are formed as floating gates. Regions 300 and302 are intercoupled by one or more metal interconnect(s) 304, havingcontacts 306 and 308, respectively, therewith. Multiple input gates106-112 are implemented as multiple active area (moat) regions 310-316,respectively. Source 102 and drain 104 are implemented in moat region318. Interposed between the poly and moat regions (not shown) is anappropriate material (e.g, gate oxide) to serve a dielectric function.

[0031] In the above embodiments of structure 100, poly regions 200, 300and 302 may be laid out in minimum width “finger” configurations toenhance performance. To further reduce depletion effects in the multipleinput moat regions, source/drain implants may be introduced to theregions. In processes where deep p+ or n+wells are available, such areasmay be used for the multiple input region(s) to further reduce depletioneffects.

[0032] In order to address the V_(t) linearity issues discussed above,regions 202-208, or regions 310-316, may be laid out as identical moat“fingers”—matched perfectly by, for example, replicating copies of asingle moat finger. For structure 100, the voltage on the floating gatemay be expressed as: $\begin{matrix}{{V_{fg} = {\sum\limits_{i}^{N}{\left( {C_{i}/C_{T}} \right) \times V_{i}}}};} & (1)\end{matrix}$

[0033] where

[0034] C_(i) is the capacitance for input i, V_(i) is the voltage atinput i, and C_(T), the total capacitance, is given by $\begin{matrix}{C_{T} = {\sum\limits_{i}^{N}C_{i}}} & (2)\end{matrix}$

[0035] In the field of mixed signal design, one especially usefulinstance of structure 100 is a two (2) input MIFG. This embodiment isillustrated in reference now to structure 400 of FIG. 4. Structure 400is a MOS transistor, comprising a source 402 and drain 404. Structure400 further comprises a first input 406 and a second input 408. FIG. 5illustrates an illustrative top-view layout of structure 400. In theembodiment illustrated in FIG. 5, a poly region 500 is formed as afloating gate. Input gates 406 and 408 are implemented as multipleactive area (moat) regions 502 and 504, respectively. Source 402 anddrain 404 are implemented in moat region 506. Floating gate 500 is laidout to effectively and efficiently couple regions 502-506, andinterposed therebetween (not shown) is an appropriate material (e.g,gate oxide) to serve a dielectric function

[0036] In the above embodiment of structure 400, poly region 500 may belaid out in a minimum width finger configuration to enhance performance.To further reduce depletion effects in the multiple input moat region,source/drain implants may be introduced. In processes where deep p+ orn+wells are available, such areas may be used for the multiple inputregion to further reduce depletion effects. In order to address theV_(t) linearity issues discussed above, regions 502 and 504 may be laidout as identical moat “fingers”—matched perfectly by, for example,replicating copies of a single moat finger.

[0037] Structures in accordance with the present invention, such asstructure 400, may be useful in a number mixed-signal devices andapplications, including: low V_(t) MOS structures for providing largesignal swing; depletion MOS structures for providing lower noise; andresistors having improved linearity. As an example, a low low V_(t) MOStransistor may be formed in accordance with structure 400, where one ofthe voltage inputs (V₂) is utilized to modulate the characteristics ofthe other input (V₁). This application exploits the capacitive couplingof the first and second input gates.

[0038] In this example, it is assumed that the standard MOS threshold isV_(t0). The threshold voltage of the first input (V_(t1)) may then bederived from equation (1), above, as:

V _(t1)=[1+(C ₂ +C ₀)/C ₁ ]×V _(t0) −C ₂ /C ₁ ×V ₂  (3)

[0039] Thus, the threshold voltage for the first input is determined bythe ratio of C₂/C₁, C₀/C₁ and, importantly, it may also be modulated bythe voltage on the second input (V₂). This relationship is hereafterdescribed in greater detail with reference to FIG. 6. In most commoncases, C₂>>C₀, thus the relationship expressed in equation (3) may berewritten as:

V _(t1)=[1+(C ₂ /C ₁)]×V _(t0) −C ₂ /C ₁ ×V ₂

[0040] When, in the layout and design of structure 400, the same gateoxide is used to separate the poly from the input gates and the MOSbody, then C₂/C₁=A₂/A₁ (i.e., the area ratio).

[0041] Referring now to FIG. 6, an illustrative plot 600 of V_(t1) as afunction of V₂ for differing C₂/C₁, assuming a V_(t0) value of 0.8volts, is depicted. Plot axis 602 depicts the value of V_(t1), whileplot axis 604 depicts the value of V₂. Plot lines 606-612 represent theresults for (C₂/C₁) values of 0, 1, 2 and 4, respectively. Asillustrated, depletion mode for V_(t1) is possible whenV₂≧[1+(C₂/C₁)]×V_(t0).

[0042] The teachings of the present invention may be readily implementedin a number of design flows and process technologies. For illustrativepurposes, however, the structures disclosed above may be formed by:performing n-well and p-well implant; utilizing a LOCOS or STI formationfor device isolation; optionally performing a high-dose (e.g., >1E15)multiple input moat implant; performing V_(t) implants for standard MOStransistors; performing gate oxidation and poly gate deposition;performing LDD and S/D implantation; and performing other necessary ordesired back-end processing with multiple level metal and passivation.

[0043] The embodiments and examples set forth herein are presented tobest explain the present invention and its practical application and tothereby enable those skilled in the art to make and utilize theinvention. However, those skilled in the art will recognize that theforegoing description and examples have been presented for the purposeof illustration and example only. The description as set forth is notintended to be exhaustive or to limit the invention to the precise formdisclosed. Many modifications and variations are possible in light ofthe above teaching without departing from the spirit and scope of thefollowing claims.

What is claimed is:
 1. A multiple input floating gate device comprising:a first input formed in a first active device region; a second inputformed in a second active device region; a floating gate disposed uponthe first and second inputs and separated therefrom by a dielectriclayer; and a device body, formed in a third active device region andcoupled to the first and second inputs through the floating gate.
 2. Thedevice of claim 1, wherein the floating gate is formed of silicon. 3.The device of claim 1, wherein each of the first and second activedevice regions are formed as a moat.
 4. The device of claim 1, whereinthe third active device region is formed as a moat.
 5. The device ofclaim 1, wherein the dielectric layer is a gate oxide.
 6. The device ofclaim 1, wherein the floating gate is formed as a single contiguous bodydisposed upon the device body and the first and second inputs.
 7. Thedevice of claim 1, wherein the floating gate is formed as multiplebodies, disposed over the first, second and third active device regions,coupled together by an interconnect.
 8. The device of claim 7, whereinthe interconnect comprises a metal layer.
 9. The device of claim 1,wherein the device functions as a transistor.
 10. The device of claim 1,wherein each input is of identical size and shape.
 11. A MOS transistor,having a dynamically adjustable threshold voltage value, comprising: afirst input formed in a first active device region; a second inputformed in a second active device region; a floating gate disposed uponthe first and second inputs and separated therefrom by a gate oxide; anda device body, formed in a third active device region and coupled to thefirst and second inputs through the floating gate.
 12. A method ofproducing a semiconductor device having a dynamically adjustablethreshold voltage value, comprising the steps of: forming a first inputin a first active device region; forming a second input in a secondactive device region; disposing a floating gate upon the first andsecond inputs with a dielectric layer interposed therebetween; andforming a device body in a third active device region, coupled to thefirst and second inputs through the floating gate.
 13. The method ofclaim 12, wherein the semiconductor device is produced in a single-polyfabrication process.
 14. The method of claim 12, wherein the floatinggate is formed of polysilicon.
 15. The method of claim 12, wherein eachof the first and second active device regions are formed as a moat. 16.The method of claim 12, wherein each active device region is ofidentical size and shape.
 17. The method of claim 12, wherein the thirdactive device region is formed as a moat.
 18. The method of claim 12,wherein the floating gate is formed as a single contiguous body disposedupon the device body and the first and second inputs.
 19. The method ofclaim 12, wherein the floating gate is formed as multiple bodiesdisposed over the first, second and third active device regions, andcoupled together by an interconnect.
 20. A method of producing amultiple input floating gate device in a single-poly MOS process,comprising the steps of: providing a substrate upon which the device isto be fabricated; performing n-well or p-well implant on the substrate;utilizing a LOCOS or STI formation for device isolation; optionallyperforming a high-dose multiple input moat implant; performing thresholdimplant; performing gate oxidation; performing poly gate deposition; andperforming source/drain implantation.